Architecture Description Languages (ADL) are used to describe the architecture of a microprocessor. An ADL description of a processor is typically utilized for designing the processor, software/hardware based verification of the processor behavior, generation of compiler tool-chain for the processor and for creating a hardware description of the processor. An ADL description describes instructions, operands, addressing modes, functional units and registers of the microprocessor. An ADL description also captures the behavior of the processor, either embedded in the processor description itself or as external functions.
Typically, an ADL captures the information about the processor in a hierarchical fashion, where instruction-groups (also called as ‘bundles’) are specified at the top-level of the hierarchy. Each bundle refers to one or more instructions, and each instruction refers to one or more operands and constant values. Similarly, each operand can contain one or more constant value or refer to other operands. Using an ADL, similar instructions, operands and bundles can be grouped together to create a more compact representation of the instruction set of the processor. Such compact representation of the instruction set is also less prone to errors because duplication of information is avoided. Also, various programming tools for the processor can be automatically generated from an ADL description of the microprocessor.
Furthermore, in order to process the ADL description of the microprocessor in a computer environment, it is necessary to parse the description and create an internal representation of the information contained in the description. The obvious way to represent this information is a tree with instruction groups (bundles) at the root, instructions at the internal nodes and operands, and constant values at the leaf of the tree. Then, a decoder for the instruction set can be constructed to traverse the hierarchy starting from the root node and visit the nodes, matching the corresponding bits at each node.
The problem with the above conventional hierarchical representation of the instruction set architecture is that it involves duplication of nodes when the same operand or constant value is referenced by many instructions or instruction groups in the architecture. Moreover, when decoding a machine instruction using the hierarchical description, the same nodes may have to be compared many times with the input, which results in increased number of comparisons when implemented in software. Such large number of comparisons in software requires similar number of comparators to be implemented in hardware. Therefore, it is desirable to provide a method, computer program and computing system for optimizing an architectural model of a microprocessor, which leads to efficient decoding of the machine code for the microprocessor. Also, such optimized architectural model results in a hardware circuit that is smaller in size and consumes lesser power when the model is transformed into hardware for the microprocessor.